The technical field of the invention is that of integrated circuit chips, in particular integrated circuit chips including vertical DRAM devices.
A conventional DRAM vertical transfer device 10 is shown in cross section in FIG. 1. A FET 11 is vertically connected between the surface bitline 12 and the buried node 13. A transfer gate 14 and an oxide interface formed of a gate oxide 15 and a trench top oxide 16 provide a MOSFET acting vertically. The MOSFET connects below the buried node 13 to a conventional deep trench storage capacitor 17. An oxide collar 18 and capacitor dielectric 19 surround the storage capacitor 17.
A support junction N+ implant 37 is provided for making ohmic contact to an n-well 38. A masked implanted N+ buried layer 39 is formed over the entire decoupling capacitor matrix. An N+ layer 40 is out diffused from each trench using conventional processes. Elements 37, 38, 39 and 40 electrically form a heavily doped N+ common outer capacitor plate with an electrical interface brought to the silicon surface through elements 38 and 37. An inner plate connection is provided by the vertical FET 11. The outer N+ plate 37 electrically isolates the bulk p-silicon 21, and thus forms an isolated p-well 42. The isolated p-well 42 is connected by using a standard CMOS p+ support junction implant 41. Shallow trench isolation regions 20 are formed on each side of the elements 37 and 41.
The conventional DRAM vertical transfer device 10 does not provide a low resistance connection to the inner plate of the capacitor 17 that bypasses the transfer MOSFET device 11. The array bitline diffusion junction 12 in conjunction with the array transistor p-well provides a series device connection whose threshold voltage is on the order of one volt. A doping profile through section 2xe2x80x942 of FIG. 1 is shown in FIG. 2. By this doping profile it can be seen that the nodes 12 and 13 are not electrically connected, and that the capacitor 17 cannot be accessed directly unless the gate 14 is turned on and the channel is inverted. The transfer device output resistance of this conventional DRAM device 10 is on the order of 100 kxcexa9, resulting in an RC time constant for a 40 fF capacitor equal to about 4 nS. This time constant is too long to be used effectively as an on-chip high frequency decoupling capacitor. The existing practice of turning on the transfer gate has the disadvantages of adding more nodes than are needed and slowing the response to the capacitor.
The present invention is directed to a structure and method for creating a vertical capacitor in a DRAM process employing an improved vertical array device cell complex.
According to a broad aspect of the present invention, an electronic structure is provided comprising an integrated circuit chip having a first capacitor and an electrical element, wherein contact to the first capacitor is through a first mechanism comprising a vertical transistor, and contact to the electrical element is through a second mechanism that differs from the first mechanism. The electrical element can be a second capacitor or an anti-fuse.
In one disclosed embodiment, the second mechanism comprises a modified doping profile within the vertical cell that provides a low resistance punch-through FET.
In another disclosed embodiment, the second mechanism comprises a pair of overlapping or nearly overlapping diffusions spaced closely enough that current transport is by punch through.
In another disclosed embodiment, the second mechanism is formed in a shallower recessed trench than the first mechanism, and includes a pair of diffusions that merge and provide a direct connection to the electrical element.